K-PAI

Silicon Valley Privacy-Preserving AI Forum

8 minute read

posted: 31-Oct-2025 & updated: 12-Nov-2025

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Invitation

Semiconductor Innovators, AI Architects, and Technology Leaders (and EVERYONE ELSE Inhabiting or Visiting Silicon Valley ★^^★)!

We are thrilled to invite you to the Thirteenth Edition of the K-PAI Forum, a premier gathering for researchers, industry leaders, and innovators exploring the frontier of privacy-first AI technologies. Following the tremendous success of our K-PAI’s 12th Chapter: Ad Intelligence - AI Revolution in Digital Marketing forum, this groundbreaking event explores the cutting edge of AI semiconductor innovation—examining how Korea and the US are leading the global race to develop next-generation AI chips, NPU architectures, and on-device AI capabilities that will power the intelligent devices of tomorrow.

Join us for an evening of transformative discussions, networking, and visionary insights at the intersection of AI innovation and semiconductor technology! This special K-PAI x K•ASIC Joint Seminar represents a historic collaboration between two pioneering organizations dedicated to advancing AI hardware innovation. Our forums have become a cornerstone for meaningful dialogue in Silicon Valley’s tech community, bringing together semiconductor engineers, AI architects, chip designers, hardware entrepreneurs, and thought leaders who are shaping the future of intelligent computing at the silicon level.

  • Please RSVP via this link!
  • Please visit K-PAI Membership to learn about our K-PAI membership for the qualification and all exclusive perks you can enjoy! and join us at K-PAI Members Kakaotalk Chatroom using this info (if you’re qualified)!

K-PAI Leader’s Perspectives

Contemporary discourse on AI ecosystems tends to focus heavily on visible layers—software services, algorithms, and applications—while overlooking the foundational infrastructure. Even within technical domains, semiconductor and hardware infrastructure constitute the essential pillars of the AI ecosystem: GPUs (Nvidia’s dominance), HBM (SK hynix’s breakthroughs), specialized AI semiconductors (NPUs, DPUs), and custom accelerators from tech giants. This landscape is increasingly shaped by geopolitical dynamics including the US-China technology competition, CHIPS Act, export controls, and supply chain restructuring. To understand and lead sustainable AI development, deep knowledge of the AI semiconductor ecosystem is absolutely essential.

The strategic partnership between K•ASIC and K-PAI transcends simple technical exchange—it illuminates the most foundational layer of the AI ecosystem while connecting Korea’s and America’s semiconductor innovation leadership. This is why we titled this forum “The AI Silicon Race: Korea-US Innovation Leadership.” This event shares the core insight that AI’s future is built not only on algorithms but on silicon, serving as a venue to explore sustainable development of the global AI ecosystem by consolidating the semiconductor capabilities of both nations.

Historic Partnership with K•ASIC

🎉 K-PAI x K•ASIC JOINT SEMINAR! 🎉

We are delighted to announce this special Joint Seminar between K-PAI and K•ASIC, representing a powerful alliance in advancing AI semiconductor innovation! This strategic collaboration bridges Korea’s world-leading semiconductor expertise with Silicon Valley’s cutting-edge AI ecosystem.

Partnership Highlights:

  • Co-hosted Event: First joint seminar showcasing Korea-US AI silicon innovation
  • Expert Speakers: Leading researchers and industry pioneers from both nations
  • Comprehensive Coverage: From AI-driven semiconductor library optimization to lightweight NPU architecture evolution
  • Premium Facilities: K•ASIC’s state-of-the-art innovation center in the heart of Silicon Valley

This partnership exemplifies the vision of creating synergistic relationships that amplify innovation while fostering international collaboration in the critical field of AI semiconductor technology. This Forum marks an exciting milestone in Korea-US tech cooperation!

We extend our sincere gratitude to K•ASIC for hosting this event at their prestigious Innovation Center, providing comprehensive event support including signage, name badges, and catering, and for this transformative partnership that will foster enhanced international collaboration in AI chip innovation.

   

Reception & Networking (5pm ~ 5:30pm)

Experience our signature networking reception in K•ASIC’s state-of-the-art facilities! This welcoming atmosphere provides the perfect setting for meaningful connections between semiconductor engineers, AI chip architects, hardware designers, and technology entrepreneurs who are pioneering the next generation of AI silicon. Light refreshments will be provided as you connect with fellow innovators in the AI hardware space.

Opening Remarks (5:30pm ~ 5:40pm)

Welcome Address

  • Speakers: K-PAI Leadership & K•ASIC Leadership
  • Time: 5:30pm ~ 5:40pm
  • slides

Join us as we officially open this historic K-PAI x K•ASIC Joint Seminar, celebrating the collaboration between two leading organizations in AI semiconductor innovation. This opening address will set the stage for an evening of cutting-edge insights into AI chip design, NPU architecture evolution, and the future of on-device AI.

Presentations (5:40pm ~ 7pm)

Main Keynote Session: From Semiconductor PPA Optimization to Physical AI - Library-Based Design Challenges and New Frontiers

  • Speaker: Naehyuck Chang, Advisor and Former EVP of Samsung Electronics
  • Time: 5:40pm ~ 6:20pm

Semiconductor design optimization has been a major source of competitiveness in the chip industry and has often had more impact than improvements in architecture or software. Even after many years of progress, the conventional layered design process still leaves room for improvement within standard cell libraries, which play a crucial role in determining power, performance, and area (PPA). The first part of this talk introduces a practical approach that uses artificial intelligence to improve cell library design and enhance PPA efficiency. The second part presents a future-oriented view of Physical AI, which combines control intelligence with physical systems, and introduces the concept of pretrained libraries, revealing new opportunities and challenges in applying library-based design and optimization methods to the next generation of intelligent physical systems.

As an ACM Fellow, IEEE Fellow, and former Technical Program Chair of the prestigious Design Automation Conference (DAC), Naehyuck brings unparalleled expertise in power and energy optimization from embedded systems to large-scale AI systems.

Sub-Session: AI Starts Here - 온디바이스 AI 시대, 경량화된 NPU 아키텍처의 진화

Richard Burroughs will present an in-depth exploration of how Neural Processing Unit (NPU) architectures are evolving to meet the demands of the on-device AI era. As AI capabilities increasingly shift from the cloud to edge devices, the need for lightweight, power-efficient NPU designs has become critical. This presentation will examine the architectural innovations enabling efficient on-device AI inference—from quantization techniques and model compression to novel dataflow architectures and memory hierarchies optimized for neural network workloads.

Richard will demonstrate how NPU architecture evolution is enabling sophisticated AI capabilities in smartphones, IoT devices, and embedded systems while maintaining strict power budgets and thermal constraints. Attendees will gain insights into the design tradeoffs between computational throughput, power efficiency, and silicon area, understanding how next-generation NPUs are being architected to support increasingly complex AI models in resource-constrained environments.

Sub-Session 2: Bridging Performance and Affordability in AI Silicon - AI 반도체 혁신, 성능과 비용의 균형을 잇다

  • Speaker: Juntaek Oh, Compiler Engineer @ HyperAccel
  • Time: 6:40pm ~ 7pm

Juntaek Oh will present insights on bridging the critical gap between performance and affordability in AI silicon design. As the AI semiconductor landscape rapidly evolves, balancing cutting-edge computational capabilities with cost-effective implementations has emerged as one of the industry’s most pressing challenges.

This presentation will explore innovative approaches to optimizing AI chip architectures that deliver high performance without prohibitive costs, examining compiler-level optimizations, hardware-software co-design strategies, and architectural innovations that maximize computational efficiency per dollar. Attendees will gain practical insights into the engineering tradeoffs and design decisions that enable scalable, economically viable AI silicon solutions for both edge devices and data center deployments.

Networking Dinner & Q&A (7pm ~ 8pm)

K-PAI Members’ favorite time! The very moment everyone awaits! — This extended networking and dinner session provides a unique opportunity to engage directly with our expert speakers and fellow attendees while enjoying a catered meal. Connect with semiconductor engineers from leading chip companies, engage with AI architects designing next-generation NPUs, and collaborate with hardware entrepreneurs building innovative AI silicon solutions. K-PAI members are encouraged to introduce themselves and their companies, creating opportunities for meaningful business connections and potential collaborations in the rapidly evolving AI hardware space. Previous forums have seen transformative partnerships emerge during these dynamic discussions, where hardware engineers, AI researchers, chip designers, and entrepreneurs bridge technical challenges with innovative solutions in real-time conversations.

Why Attend?

Attending this landmark K-PAI x K•ASIC Joint Seminar offers a rare opportunity to explore the cutting edge of AI semiconductor innovation from world-class researchers and industry practitioners. You’ll gain essential insights into AI-driven semiconductor library optimization from leading experts in design automation, discover how NPU architectures are evolving to enable efficient on-device AI, and understand the technical challenges and solutions shaping the future of AI chip design. This forum bridges academic research with practical industry implementation, providing actionable frameworks for building next-generation AI hardware. Engage with thought leaders from both Korea and the US who are pioneering new approaches to AI silicon design that will power the intelligent devices of tomorrow.

Target Audience

The event is tailored to a diverse yet focused audience. It caters to:

  • Semiconductor engineers and chip designers
  • AI hardware architects and researchers
  • NPU and accelerator designers
  • ASIC and FPGA engineers working on AI workloads
  • Embedded systems engineers
  • Hardware-software co-design specialists
  • Computer architecture researchers
  • Physical design and verification engineers
  • AI system engineers
  • Hardware technology entrepreneurs and investors
  • Engineering managers in semiconductor and AI companies
  • Product managers for AI hardware solutions
  • Academic researchers in computer engineering and electrical engineering
  • Anyone interested in the intersection of AI innovation and semiconductor technology

Note: This announcement page will be updated as additional speakers are confirmed. Please check back regularly for the latest information, or follow our updates on the Luma registration page.

We look forward to your participation in this transformative K-PAI x K•ASIC Joint Seminar! If you have any questions or topics you’d like to discuss, please don’t hesitate to reach out at sunghee.yun@gmail.com.

Best regards,

K-PAI Committee

Updated:

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